MediaTek MT8163 platform datasheet (Part III) data download 1. Show Read Direct Memory Access 1.1.1 Introduction The RDMA engine is responsible for providing data to the interface engine, such as DSI, DBI, and DPI. Since the interface engine requires real-time services, the RDMA engine contains a single line of buffer T. o Store enough pixel data. It also detects the usage of data buffers, which triggers EMI's deep sleep mode.

1.1.2 Features Direct link input mode Memory input mode  Input format: YUYV 422, UYVY 422, YVYU 422, UYVY 422, RGB 565, RGB 888, ARGB 8888  Input Footprint: Raster Scan Mode, 64 Byte Aligned Tile Mode  Deceleration mode [Through] yield control  Byte swapping, RGB swapping  Progressive, staggered  Programmable YUV to RGB matrix  If the data buffer is in a running state, the output mode is not stopped. Buffer controllers  240x16 byte data buffer (1280 pixels, RGB 888 format)  Programmable request/pre-over/overshoot control mechanisms 1.1.3 Block Diagram The following diagram shows a detailed block diagram of the RDMA engine. The clock is automatically configured, and the output clock domain uses an asynchronous FIFO.


1.1.4 Register Definition
Module name: DISP_RDMA Base aDDRess: (+14009000h)

Module name: DISP_RDMA Base address: (+14009000h)