MediaTek 5G Chip MT6985 (Dimensity 9200) Datasheet | Edal Tech International Limited

2024.12.04

MediaTek 5G Chip MT6985 (Dimensity 9200) Datasheet

Technical Blog

The MediaTek MT6985 device is a highly integrated baseband platform that integrates a modem and application processing subsystem to support LTE/LTE-A/NR-Sub6 and C2K smartphone applications. The chip integrates four Arm® Makalu (ELP) cores, four Arm® Klein cores, and a powerful multi-standard video codec. In addition, an extensive set of interfaces and connectivity peripherals are included for connection with cameras, touchscreen displays, and UFS/MMC/SD cards. Multi-core Arm® Makalu, Arm® Klein applications processors equipped with NEON engines provide the necessary processing power to support the latest OpenOS and its demanding applications such as web browsing, email, GPS navigation, and gaming. All content is viewable on a high-resolution touchscreen, enhanced with 2D and 3D graphics acceleration. In addition, multi-standard video accelerators and advanced audio subsystems are integrated to provide advanced multimedia applications and services such as streaming audio and video, multiple decoders and encoders. The combination of high-performance CPU, DSP, and hardware coprocessor provides a powerful modem subsystem capable of supporting NR Sub6, LTE Cat 19, Category 24 HSDPA downlink, and Category 7 HSUPA uplink data rates, as well as Class 12 GPRS, EDGE The MT6985 also contains Wireless Communication devices, including WLAN, Bluetooth, and GPS. With the Combo chipset's four advanced radio technologies, the MT6985 provides the industry's best and most convenient connectivity solution.

Achieve higher overall quality when voice, data, and audio/video are transmitted simultaneously on mobile phones and media tablets. Small footprint and low power consumption greatly reduce PCB layout resources.

1.1 Prominent Features of MT6985 Integration - 1 x Arm® Makalu-ELP core operating at > 2.85 GHz - 3 Arm® Makalu cores operating at > 2.4 GHz - 4 Arm® Klein cores operating at 1.8 GHz - LPDDR5/LPDDR5X up to 24 GB (4 lanes, 16-bit data bus width) - Memory clocks up to LPDDR5-6400/LPDDR5X-8533 - LTE cat-19 4x4 MIMO - NR Sub6 4CC，300 MHz BW - Resolution up to QHD+ (1,440 x 3,360) - OpenGL ES 3.2/Vulkan 1.2 3D graphics accelerator - ISP supports 80 MP@30 fps. - AV1 8K@30 fps decoder - HEVC 8K@30 fps decoder - HEVC 8K@30 fps encoder - Voice codecs (FR, HR, EFR, AMR FR, AMR HR, and wideband AMR and EVS_WB) 图 1-1. MT6985 高级功能框图.png

Figure 1-1. MT6985 Advanced Functions Block Diagram 1 1.2 Platform Features -general - Smartphone, 2 MCU subsystem architectures - Support for UFS boot - Support LPDDR5/LPDDR5X - AP MCU subsystem - 1 x Arm® > 2.85 GHz Makalu-ELP core with 64 KB L1 I cache, 64 KB L1 D cache, and 1 MB L2 cache - 3 Arm® > 2.4 GHz Makalu cores, each with 64 KB L1 I cache, 64 KB L1 D cache, and 512 KB L2 cache - 4 Arm® 1.8 GHz Klein cores, each with 64 KB L1 I cache, 64 KB L1 D cache, and 256 KB L2 cache (2 Klein cores share 512 KB L2 cache.) ） - Shared 8 MB L3 cache - NEON multimedia processing engine with support for SIMDv2/VFPv4 ISA - DVFS technology, with Makalu-ELP cores operating from 0.65V to 1.05V and Makalu cores and Klein cores operating from 0.55V to 1.05V. - MediaTek Vision Processor Unit (MVPU) for CV and NN - Maximum performance: Fix8: up to 2.6 TOPS; Fix16: Up to 0.65 TOPS; FP16: UP TO 0.65 TOPS; FP32: Up to 0.16 TOPS - C, OpenCL, and Halide programming languages - Advanced software framework for automated archiving and convergence - Enhanced data sharing for CV/NN algorithms - Local transcendence functions for special operations - Vector FPUs that support applications that require high accuracy

- 512 KB local memory (L1 memory)

- MediaTek Deep Learning Accelerator (MDLA) supports high-performance, energy-efficient NN applications and high energy efficiency - Maximum Performance: 8(A) x 8(W) 20.8 TOPS, 16(A) x 8(W) 10.4 TOPS, 16(A) x 16(W) 5.2 TOPS, FP16/BF16 5.2 TOPS - Synchronous pipeline hardware function blocks (convolution/action/pooling/EWE/linear) - Support for sparse-aware convolutions to skip extra MAC cycles - Enhanced layer convergence to further reduce DRAM/TCM memory bandwidth - Support for Android NN Asymmetric Quantized Data format - Support for compression activations and weights to reduce DRAM BW - High-quality AI videos with high energy efficiency - APU memory subsystem - L2 data memory scenario-based allocation policy, up to 8 MB - eDMA reduces the extra time required for data transfer - MD MCU subsystem - High-performance multi-core and multi-threaded processor architecture - High-performance AXI bus interface - A general-purpose DMA engine and a dedicated DMA channel are used for peripheral data transfer - Power management for clock gating - MD external interface - Dual SIM/USIM interfaces - Interface pins to RF and radio-related peripherals (antenna tuners, PAs, etc.). -security

- Arm® TrustZone® security

- External memory interface - LPDDR5/LPDDR5X up to 24 GB (4 lanes, 16-bit data bus width) - Memory clocks up to LPDDR5-6400/LPDDR5X-8533 - Self-refresh/partially self-refresh mode - Low-power operation - Programmable slew rate for memory controller I/O pads - Dual-channel memory devices - Advanced bandwidth quorum control -peripheral - 1 USB port with USB 3.0 host/device mode or USB 2.0 OTG mode; 1 port with USB2.0 OTG mode - UFS 4.0 2-channel - 4 UARTs for debugging and application - 8 SPI master ports for external devices, one of which supports QSPI. - 9 I2Cs/5 I3Cs for controlling peripherals such as CMOS image sensors, LCM or FM receiver modules - Up to 4 PWM channels (4 PWM channels depending on system configuration and I/O usage) - GPIO - 1 set of memory card controllers with SDIO 3.0 support - Operating conditions - Core voltage: 0.55~0.825V - Input/output voltage: 1.8V - LCM interface 1.8V - Clock source: 26 MHz, 32.768 kHz -encapsulation - Type: HBPOP HBPOP - 14.5 mm x 14 mm - Height: 0.68 mm max (no DRAM on top) - Number of balls 1283 balls - Ball spacing: 0.35 mm