MediaTek MT6190M 5G RF System Datasheet | Edal Tech International Limited

2024.12.04

MediaTek MT6190M 5G RF System Datasheet

Technical Blog

MediaTek MT6190M is a multimode, multiband, and highly integrated transceiver with a 12 nm FinFET CMOS. MT6190M RF system data sheets describe the performance goals for RF standalone chips to be embedded throughout the platform.

directory 1 Introduction 1.1 Overview 1.2 Main features 2 Block Diagram and Application Diagram 3 General Specifications 3.1 Packaging 3.2 Ordering Information and IC Marking 3.3 MT6190M I/O List 3.4 Ball Distribution 3.5 Absolute Maximum Ratings 3.6 Operating Conditions 4 Supply Specifications 4.1 External Power Supplies and Interfaces 5 Transmitters 5.1 TX Block Diagram 5.2 NR/4G FDD/TDD transmit chain performance specification 5.3 3G FDD Transmit Chain Performance Indicators 5.4 3G TDD Transmitter Chain Performance Specification 5.5 3G C2K Transmit Chain Performance Specification 5.6 2G Transmit Chain Performance Specification 5.7 MRx Performance Specifications 6 RF receiver 6.1 TD-SCDMA Acceptance Specifications 6.2 GGE (2G GSM/GPRS/EDGE) receive specifications 6.3 CDMA Acceptance Specifications 6.4 WCDMA Reception Specification 6.5 LTE Reception Specifications 6.6 NR RX Specifications 7 digital control interfaces 7.1 Introduction 7.2 Power-on reset 7.3 Digital Mode of Operation 8 Refer to the clock specification 8.1 Reference Input Buffer Specification (CLK26M) 8.2 26 MHz Clock Specification Appendix 1 Terms and Conditions Figure 2-1 RFSYS block diagram Figure 3-1 Globe Diagram Figure 5-1 TX Block Diagram (TX0) Figure 6-1 Receiving Block DiagramMT6190M Block diagram and application diagram

SerDes interface model Use the provided SerDes IBIS model to represent this high-speed interface. The following table summarizes the PCB trace requirements for the SerDes interface between the RF and AP chips.

Routing guideline		AP chip	RF chip
Impedance	Differential	75~100 ohm (including ±10%), typical case Suggestion: 85±10% ohm or 90±10% ohm
	Single end	37.5~50 ohm (including ±10%), typical case example Suggestion: 42.5±10% ohm or 45±10% ohm
Lane skew	Intra	≤ 1 ps (≈6 mil@FR4 material)
	Inter	≤ 160 ps (≈960 mil@FR4 material) (data to clock in UL and DL respectively)
Lane sensitivity	To other lanes	≥ 3 x W (inner layer) [Exception] ≥ 2W under chip fanout area (inner layer)
	To other traces	≥ 4 x W (inner layer with GND trace) [Exception] ≥ 3W under chip fanout area (inner layer with GND trace)
ESD interference		Place GND trace with high density GND via; route in inner layer Adjacent vertical layers with SerDes routing must be full GND plane.
Routing layer		Must be the same for all lanes.
Loss budget		≤ 4 dB@6 GHz (typical length ≤ 8 cm@2.5 mil trace width)
Lane via	Quantity (max.)	x3 (x2 buried + x1 blind) Reserve GND via adjacent to lane via to optimize the return path.
	Type/Size	Buried: 100/23 0um; blind: 250/450 um
	Stub	No
Power	AVDD12_DRF	Power inductance: < 1 nH (ball to 1st cap) External capacitor: 1 nF + 100 nF - Distance between ball and cap ≤ 100 mil - Power trace width ≥ 15 mil - No power via between ball and cap	Power inductance: < 1 nH (ball to 1st cap) External capacitor: 1 nF + 100 nF - Distance between ball and cap ≤ 100 mil - Power trace width ≥ 20 mil - No power via between ball and cap
	AVDD18_DRF	Power inductance: < 1 nH (ball to 1st cap) External capacitor: 100 nF - Distance between ball and cap ≤ 100 mil - Power trace width ≥ 20 mil - No power via between ball and cap	Power inductance: < 1 nH (ball to 1st cap) External capacitor: 100 nF - Distance between ball and cap ≤ 100 mil - Power trace width ≥ 20 mil - No power via between ball and cap

MT6190M IC Mark
MT6190M IC标记

External power supply and interface MT6190M Powered by seven power sources.

Supply name	Usage	Regulator type	Output voltage
VRF18	LDO supply (from system DCDC) for all major sub- systems, interface and register retention	Linear with ripple	1.8V
VRF13	DCDC supply for all major sub- systems	Linear with ripple	1.3V
VRF09	DCDC supply for all major sub- systems	Linear with ripple	0.9V
VIO18	LDO supply (from system DCDC) for all major sub- systems	Linear with ripple	1.8V
VIO12	LDO supply (from system DCDC) for all major sub- systems	Linear with ripple	1.2V
DVDD_DRF	DCDC supply for all major sub- systems	Linear with ripple	0.7V
DVDD_MEM	LDO supply (from system DCDC) for all major sub- systems	Linear with ripple	0.85V

MT6190M 电源引脚

TX block diagram MT6190M contains two separate emitters, TX0 and TX1, to support both CA and MIMO situations. The following diagram is a block diagram (TX0). The LB/MHB/CB block is the same between TX0 and TX1, except that TX1 does not support 2G.
TX框图（TX0）