1. System overview The MediaTek MT6983 (see Figure 1-1) integrates Bluetooth, FM, WLAN, and GPS modules and is a highly integrated baseband platform that integrates a modem and application processing subsystem to support LTE/LTE-A/NR and C2K smartphone applications. The chip integrates four Arm® Matterhorn (ELP) cores, four Arm® Klein cores, and a powerful multi-standard video codec. In addition, an extensive set of interfaces and connectivity peripherals for connecting cameras, touchscreen displays, and UFS/MMC/SD cards are included. The application processors are multi-core Arm® Matterhorn, Arm® Klein, and are equipped with the NEON engine, which provides the processing power needed to support the latest OpenOS and its demanding applications such as web browsing, email, GPS navigation, and gaming. All content can be viewed on a high-resolution touchscreen display, and graphics are enhanced with 2D and 3D graphics acceleration. Multi-standard video accelerators and advanced audio subsystems are also integrated to provide advanced multimedia applications and services, such as streaming audio and video, multiple decoders and encoders. The combination of high-performance CPU, DSP, and hardware coprocessor provides a powerful modem subsystem capable of supporting NR Sub6, LTE Cat 19, Category 24 HSDPA downlink, and Category 7 HSUPA uplink data rates, as well as Category 12 GPRS, EDGE. The MT6983 also contains Wireless Communication devices, including WLAN, Bluetooth, and GPS. The MT6983 integrates four advanced radio technologies into a single chip, providing the industry's best and most convenient connectivity solution. Improves the overall quality of simultaneous transmission of voice, data, and audio/video on mobile phones and media tablets. The small footprint and low power consumption greatly reduce PCB layout resources.


1. Highlights of MT6983 integration • 1 x Arm® Matterhorn-ELP core operating at > 2.85GHz • 3 Arm® Matterhorn cores operating at > 2.4 GHz • 4 Arm® Klein cores running at 1.8 GHz • LPDDR5/LPDDR5X up to 24 GB (4 channels, 16-bit data bus width) • Memory clocks up to LPDDR5-6400/LPDDR5X-7500 • LTE cat-19 4x4 MIMO • NR Sub6 3CC with 300 MHz bandwidth • Embedded connectivity systems, including WLAN/BT/FM/GPS • Resolution up to QHD+ (1,440 x 3,360) • OpenGL ES 3.2 3D graphics accelerator • ISP supports 80 MP @30 fps. • AV1 8K @30 fps decoder • HEVC 8K @30 fps decoder • HEVC 4K @60 fps encoder • Voice codecs (FR, HR, EFR, AMR FR, AMR HR, and wideband AMR and EVS_WB)

Figure 1-1 Block diagram of the MT6983 advanced functions 2. Platform functions • General − Smartphone, 2 MCU subsystem architectures − Support UFS start-up − Support LPDDR5/LPDDR5X • AP MCU subsystem − 1 Arm® > 2.85 GHz Matterhorn-ELP core with 64 KB L1 I cache, 64 KB L1 D cache, and 1 MB L2 cache − 3 Arm® > 2.4 GHz Matterhorn cores, each with 64 KB L1 I cache, 64 KB L1 Dcache, and 512 KB L2 cache − 4 Arm® 1.8 GHz Klein cores with 64 KB L1 I cache, 64 KB L1 D cache, and 256 KB L2 cache each (2 Klein cores share 512 KB L2 cache) − Shared 8 MB L3 cache − NEON multimedia processing engine with support for SIMDv2/VFPv4 ISA − DVFS technology, the Matterhorn-ELP core has an adaptive operating voltage of 0.65V to 1.05V, and the Matterhorn core and Klein core have an adaptive operating voltage of 0.55V to 1.05V • MediaTek Vision Processor Units (MVPUs) for CV and NN − Top performance: Fix8: up to 2.3 TOPS; Fix16: Up to 0.56 TOPS; FP16: up to 0.56 TOPS; FP32: Up to 0.14 TOPS − C, OpenCL and Halide programming languages − Advanced software framework for automated archiving and convergence − Enhanced data sharing for CV/NN algorithms − Native transcendence functions for special operations − Vector FPUs support applications that require high accuracy − 512 KB local memory (L1 memory) • MediaTek Deep Learning Accelerator (MDLA) for high-performance and power-efficient neural network applications − Top performance: 8(A) x 8(W) 16.4 TOPS, 16(A) x 8(W) 8.2 TOPS, 16(A) x 16(W) 4.1 TOPS, FP16/BF16 4.1 TOPS − Synchronous pipeline hardware function blocks (CONV/ACT/POOL/EWE/BILINEAR)
− Support for sparse-aware convolutions to skip redundant MAC cycles − Enhanced layer convergence to further reduce DRAM/TCM memory bandwidth − Support Android NN asymmetric quantization data format − Support for compression activations and weights to reduce DRAM BW • Memory subsystem in APUSYS − Level 2 data memory: scenario-based allocation strategy, up to 8 MB − eDMA reduces the extra time required for data transfer • MD MCU subsystem − High-performance multi-core and multi-threaded processor architecture − High-performance AXI bus interface − Generic DMA engine and dedicated DMA channel for peripheral data transfer − Power management for clock gating control • MD external interface − Dual SIM/USIM interfaces − Interface pins to RF and radio-related peripherals (antenna tuners, PAs, etc.). •safe − Arm® TrustZone® security • External memory interface − LPDDR5/LPDDR5X up to 24 GB (4 channels, 16-bit data bus width) − Memory clocks up to LPDDR5-6400/LPDDR5X-7500 − Self-refresh/partially self-refresh mode − Low-power operation − Programmable slew rate of memory controller I/O pads − Dual-column storage devices − Advanced bandwidth quorum control •peripheral device − PCIe 2 port with Gen3 1-lane RC mode − 1 USB port supports USB 3.0 host/device mode or USB2.0 OTG mode, and 1 port supports USB 2.0 OTG mode − UFS 3.1 2-channel − 4 UARTs for debugging and application − 8 SPI hosts for external devices, 1 of which supports QSPI − 9 I2C/5 I3C for control peripherals such as CMOS image sensors, LCM or FM receiver modules − Up to 4 PWM channels (depending on system configuration and I/O usage)
− GPIO − 1 set of memory card controllers, supporting SDIO 3.0 protocol • Operating conditions − Core voltage: 0.55~0.75V − Input/output voltage: 1.8V − LCD interface: 1.8V − Clock source: 26 MHz, 32.768 kHz •encapsulation − Type: HBPOP − 14 mm x 14 mm − Height: Typical. 0.59 mm (without DRAM on top) − Balls: 977 balls − Ball spacing: 0.35 mm 3. Features of the modem • NR − 3GPP EN-DC option 3/3a/3x – 3GPP SA Option 2 − FDD/TDD up to 7.01 Gbps downlink and 2.5 Gbps uplink − Support for Downlink Carrier Aggregation (CA): 5100 MHz RF bandwidth per component carrier (CC), up to 3CC, 300 MHz total bandwidth − Support for Uplink Carrier Aggregation (CA): 5100 MHz RF bandwidth per component carrier (CC), up to 2CC, total bandwidth 200 MHz − Supports SCS 15/30 kHz − Supports downlink/uplink 256 QAM − Supports downlink 4x4 MIMO and uplink 2x2 MIMO • LTE − FDD/TDD up to 1.6 Gbps downlink and 211 Mbps uplink − Downlink Carrier Aggregation (CA) Capability; Each component carrier (CC) has 1.420 MHz RF bandwidth with a maximum of 5 CC − Upband in-carrier aggregation (CA) capability; Each component carrier (CC) has 1.420 MHz RF bandwidth with up to 2 CCs − Supports downlink/uplink 256 QAM – 4x2 downlink SU-MIMO per component carrier − Downlink MU-MIMO for each component carrier − Support for MBMS − Uplink CoMP capability − Advanced interference cancellation ▪ PDCCH pIRC ▪ CRS-based PDSCH ▪ DMRS-based Co-UE − Selection of transmitting antennas
• Features supported by 3G UMTS FDD − 3G modems support most of the major features in 3GPP release 7 and Release 8 − CPC (DTX, UL DRX DL DRX in CELL_DCH), HSSCCH-LESS, HS-DSCH − Dual-battery operation − MAC-ehs − 2 DRX (Receiver Diversity) schemes in URA_PCH and CELL_PCH − Uplink cats. 7 (16 QAM) with a throughput of up to 11.5 Mbps − Downlink cats. 24 (64 QAM, dual-cell HSDPA) with up to 42.2 Mbps throughput − Rapid hibernation − ETWS − Network selection enhancements − Selection of transmitting antennas • Radio interface and baseband front-end − IQ data via high-speed serial interface (DigRF) between RF and baseband chip − Programmable radio reception filter with adaptive gain control − Dedicated Rx filter for FB acquisition − Baseband Parallel Interface (BPI) and MIPI RFFE interfaces with programmable drive strength − Multi-band support • GSM modem and voice codec − Dial tone generation − Noise reduction − Echo suppression − Advanced sidetone oscillation suppression − Digital sidetone generator with programmable gain − 2 programmable acoustic compensation filters − GSM quad vocoder for Adaptive Multi-Rate (AMR), Enhanced Full Rate (EFR), Full Rate (FR), and Half Rate (HR). − GSM channel coding, equalization and A5/1, A5/2 and A5/3 encryption − GPRS GEA2 and GEA3 encryption − Programmable GSM/GPRS/EDGE modem − Packet-switched data using CS1/CS2/CS3/CS4 coding schemes − GSM circuit-switched data − GPRS/EDGE Class 12 − Support for SAIC (Single Antenna Interference Cancellation) technology − VAMOS (Voice Service with Adaptive Multi-User Channels on One Slot) technology in the R9 specification − Selection of transmitting antennas − RF dual antenna reception
• CDMA2000 modem interface − Support for CDMA2000 1xRTT (version 0) and CDMA2000 HRPD/1xEV-DO revisions 0 and A − Forward and reverse links support a maximum 1x data rate of 153.6 kbps, forward links support a DO data rate of 3.1 Mbps, and reverse links support 1.8 Mbps − Hybrid operation between 1x and HRPD − Simultaneous Hybrid Dual Receiver (SHDR) support − Support for 1x diversity − Support for SRLTE − Selection of transmitting antennas