2024.12.04

MediaTek MT7933CT Datasheet

The MediaTek MT7933CT is a highly integrated single chip with an ARM® Cortex-M33 applications processor, a low-power 1x1 802.11a/b/g/n/ac/ax dual-band Wi-Fi subsystem, a Bluetooth v5.0 subsystem, an audio subsystem with a cadence® Tensilica® HIFI4 processor, and a power management unit (PMU). The Wi-Fi subsystem and the Bluetooth v5.0 subsystem provide feature-rich, high-standard wireless connectivity and reliable, cost-effective throughput over long distances. The optimized RF architecture and baseband algorithm provide superior performance and low power consumption. MT7933CT is designed to support standards-based functionality in the areas of safety, quality of service, and international regulations to deliver the best performance to end users at all times, in any situation. MT7933CT Based on the ARM® Cortex-M33 with a floating-point microcontroller (MCU), including SRAM/ROM memory. The chip also supports a rich set of peripheral interfaces, including USB2.0, SDIO, SPI master, SPI slave, I2C, I2S, IR input, UART, AUXADC, PWM, and GPIO.

Basic features: Wi-Fi • IEEE 802.11 1T1R a/b/g/n/ac/ax 5 GHz and 2.4GHz bands • Support 1x1 20 MHz bandwidth, MCS0~8(256-QAM) 2.4/5 GHz band • Support MU-MIMO reception • Supports uplink MU-ODMA TX and downlink MU-ODMA RX • Supports Tx LDPC (Low Density Parity) • Support for Rx Beamformee • Support receiving STBC • Wi-Fi Security WFA WPA/WPA2/WPA3 Personal • QoS support for WFA WMM • Integrated balun, PA, LNA, and T/R switches • CSI (Channel Signal Information) support • Antenna diversity support • Optional external LNA and PA support

Bluetooth • BT5.2 LE sync channel • BT5.1 Ad Enhancements • BT5.0 2M_PHY / Long Range / AD Extension / SAM / CS#2 / High Duty Cycle Not Connected ADV • BT4.2 Link Layer Privacy/LE Secure Connection/LE Packet Length Extension/Link Layer Extension Scanner Filtering Policy • BT4.1 Link Layer Topology/Secure Connection • BT4.0 and below BR/EDR • BR/EDR and BLE dual-mode concurrency • Integrated balun and PA • Decentralized network support: Up to 7 picones for background query/paging scanning at the same time • Up to 4 BT links + 8 BLE links • Support SCO and eSCO link retransmission • Packet loss concealment • Channel quality-driven data rate adaptation • Channel evaluation and WB RSSI for AFH Microcontroller subsystem • ARM® Cortex-M33® with floating point unit (FPU) at 300 MHz • Supports 12 DMA channels • Embedded 8MB UHS SRAM for applications • Supports external serial flash memory in quad peripheral interface (QPI) mode • Support for Execution-in-Place (XIP) over flash • Supported interfaces: USB2.0, SDIO, SPI Master, SPI Slave, I2C, I2S, IR Input, UART, AUXADC, PWM, and GPIO Audio subsystem • Cadence ® Tensilica® HiFi4 processor clocked at 600 MHz • audio codec with 3 ADC and 2 DAC channels Secure boot and encryption engine • Secure boot from serial flash • Hardware cryptographic engines, including AES, DES/3DES, and SHA Clock source • 26MHz crystal oscillator • 32-kHz external crystal oscillator or internal 32-kHz crystal oscillator for RTC miscellaneous • Advanced TDD Wi-Fi/Bluetooth coexistence solution Block diagram
MT7933CT 片上系统框图
Figure 1-1 MT7933CT System-on-Chip Block Diagram