2024.12.03

MediaTek MT8395/i1200 AIoT Application Processor Technical Brief

1. System overview

The MediaTek i1200/MT8395 device (see Figure 1-1) is a highly integrated platform that includes an application processing subsystem and an AI accelerator (AIA) application. The chip integrates four ARM® Cortex-A78 cores operating up to 2.2 GHz, four ARM® Cortex-A55 cores operating up to 2.0 GHz, and a powerful multi-standard video codec. In addition, interface cameras, touchscreen displays, and UFS/SD cards contain a large number of interfaces and connected peripherals.

The application processors are multi-core ARM® Cortex-A78, ARM® Cortex-A55 with NEON engine, which provide the processing power needed to support the latest OpenOS and its demanding applications such as smart appliances, industrial IoT, and other AI-embedded devices.

All of this is viewed on a high-resolution touchscreen display and enhanced with 3D graphics acceleration.

Multi-standard video accelerators and advanced audio subsystems are also integrated to provide advanced multimedia applications and services, such as streaming audio and video, a large number of decoders and encoders.

The overall quality of simultaneous voice, data, and audio/video transmission on AI-embedded devices has been improved.



1.1 Outstanding features of i1200/MT8395 integration


4 ARM® Cortex-A78 cores operating at 2.2 GHz


4 ARM® Cortex-A55 cores operating at 2.0 GHz


LPDDR4X Up to 16 GB (four channels, 16-bit data bus width)


Memory data rates up to LPDDR4X-4266


Resolution up to dual 4K60 display outputs


OpenGL ES 3.2 3D graphics accelerator


The ISP supports 48MP@30 fps sensors, YUV throughput: 350 MP/s


AV1 4K@90 fps decoder


HEVC 4K@90 fps decoder


HEVC 4K@60 fps encoder

图 1-1 高级 MT8395 功能框图
Figure 1-1 Block diagram of the advanced MT8395 functions

1.2 Platform Features

So so


 Smart camera/display, two MCU subsystem architectures

         Support eMMC/UFS/USB/SPINOR boot

         Support LPDDR4X


AP MCU subsystem


 4 ARM® 2.2 GHz Cortex-A78 cores, each with 64 KB L1 I-cache, 64 KB L1 D cache, and 256 KB L2 cache

         4 ARM® 2.0 GHz Cortex-A55 cores, each with 32 KB L1 I-cache, 32 KB L1 D cache, and 128 KB L2 cache

         Share 2 MB L3 cache

         NEON multimedia processing engine with support for SIMDv2/VFPv4 ISA

         DVFS technology with adaptive operating voltage from 0.55V to 0.975V


Computing and multimedia engines


 Mali G57 MC5

         Deep Learning Accelerator (MDLA for AIA)

         Vision Processor Unit (VP6 of VPU)

         Image Signal Processing (ISP)

         HIFI-256 with 4 KB TCM

          RISC-V (MTK RV33)

         Display (HDR10)

         Video codec (H.264/HEVC/VP9/AV1)


Programmable Vision Processor Unit (VPU) for AI and CV


 Top performance: Fix8: up to 426 GMAC;

                          Fix16: Up to 106 GMACs;

                          FP16: up to 53 GMAC,

                          FP32: Up to 27 GMACs

         Dual-core supports multiple applications at the same time

         vFPU supports applications that require high accuracy


The AI Accelerator (AIA) (Deep Learning Accelerator: DLA) supports NN applications with high compute demands


 Top performance: Fix8 1966 GMAC, Fix16 983 GMA

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Figure 2-1 LPDDR4X Spherical Chart View