The MediaTek MT8781 device (see Figure 1-1) integrates Bluetooth, FM, WLAN, and GPS modules and is a highly integrated baseband platform that integrates a modem and application processing subsystem to support LTE/LTE-A and C2K tablet applications. The chip integrates two Arm® Cortex-A76 cores running at up to 2.2 GHz, six Arm® Cortex-A55 cores running at up to 2.0 GHz, and a powerful multi-standard video codec. In addition, an extensive set of interfaces and connectivity peripherals for connecting cameras, touchscreen displays, and UFS/MMC/SD cards are included.

1. System overview

The application processors are multi-core Arm®Cortex-A76, Arm®Cortex-A55 with NEON engine, which provides the processing power needed to support the latest OpenOS and its demanding applications such as web browsing, email, GPS navigation, and gaming. All content can be viewed on a high-resolution touchscreen display, and graphics are enhanced with 2D and 3D graphics acceleration.

Multi-standard video accelerators and advanced audio subsystems are also integrated to provide advanced multimedia applications and services, such as streaming audio and video, multiple decoders and encoders.

The MT8781 provides a powerful modem subsystem that supports LTE downlink category 13, LTE uplink category 7, as well as WCDMA, CDMA2000 1xRTT/EVDO, GSM/EDGE.

The MT8781 also embodies Wireless Communication devices, including WLAN, Bluetooth, and GPS. The MT8781 integrates four advanced radio technologies into a single chip, providing the industry's best and most convenient connectivity solution.

The overall quality of voice, data, and audio/video simultaneous transmission on phones and tablets has been improved. The small footprint and low power consumption greatly reduce PCB layout resources.

1.1 Prominent Features of MT8781 Integration

2 Arm cortex-a76®cores operating at 2.2 GHz

6 Arm cortex-a55®cores operating at 2.0 GHz

Up to 12GB LPDDR4X-4266 SDRAM (2 lanes, 16-bit data bus each)

LTE Cat-13

Embedded connectivity systems, including WLAN/BT/FM/GPS

Resolution up to 2K (2,000 x 1,200)

OpenGL ES 3.2 3D graphics accelerator

The ISP supports 32 MP@30 fps

H.265 2560 x 1,440@30 fps decoder

H.265 2560 x 1,440@30 fps encoder

Speech codecs (FR, HR, EFR, AMR FR, AMR HR, wide-band AMR, and EVS_WB)

Figure 1-1 Block diagram of the MT8781 advanced functions

1.2 Platform Features

So so

− Smartphone, 2 MCU subsystem architectures

− Support eMMC/UFS start-up

− Support LPDDR4X

AP MCU subsystem

− 2 x Arm® 2.2 GHz Cortex-A76 cores, each with 64 KB L1 I cache, 64 KB L1 D cache, and 256 KB L2 cache

− 6 Arm® 2 GHz Cortex-A55 cores, each with 32 KB L1 I cache, 32 KB L1 D cache, and 128 KB L2 cache

− Share 1 MB of L3 cache

− NEON technology, advanced SIMDv2 for accelerated multimedia processing

− Vector floating-point coprocessor extension, VFPv4

− DVFS technology, adaptive operating voltage from 0.55V to 0.9V

MD MCU subsystem

− High-performance multi-core multi-threaded processor architecture

− High-performance AXI bus interface

− Generic DMA engine and dedicated DMA channel for peripheral data transfer

− Power management for clock gating control

MD external interface

− Dual SIM/USIM interfaces

− Interface pins to RF and radio-related peripherals (antenna tuners, PAs, etc.).

safe

− Arm® TrustZone® security

− Inline engine for Full Disk Encryption (FDE) and File-Based Encryption (FBE).

− MediaTek CryptoCore

External memory interface

− Up to 12 GB of LPDDR4X-4266 SDRAM

− 2 channels, each with a 16-bit data bus

− Support for dual-row devices

− Support for Self-Refresh/Partial Array Self-Refresh (PASR) commands

− High-level command arbitration

− Well-designed power reduction technology

peripheral device

− USB2.0 OTG mode

− eMMC5.1

- UFS 2.2

− 3 UARTs for debugging and application

− 6 SPI hosts for external devices

− 3 I2C/7 I3C for controlling peripherals such as CMOS image sensors, LCM or FM receiver modules

− Maximum. 3 PWM channels (depending on system configuration and I/O usage)

− I2S for connecting an optional external high-end audio codec

− GPIO

− 2 sets of memory card interfaces, supporting SD/SDHC/MMC and SDIO2.0/3.0 protocols

Operating conditions

− Core voltage: 0.55V/0.6V/0.65V/0.725V

− Input/output voltage: 1.8V/2.8V/3.3V

− Memory: 0.75V

− LCD interface: 1.8V

− Clock source: 26 MHz, 32.768 kHz

encapsulation

− Type: FCCSP

− 11.35 mm x 11 mm

− Height: Maximum. 0.9 mm

− Number of balls: 806 balls

− Ball spacing: 0.35 mm

2. Product description

2.1 Pin Description

2.1.1 Spherical view

Figure 2-1 LPDDR4X Spherical Chart View